Sheet resistivity can vary in an interconnect metal layer as a result of variations in trench width or trench depth that can occur during formation of interconnect lines. By way of background, sheet resistivity of an interconnect metal layer is measured in “ohms per square” of the interconnect surface. Variations in sheet resistivity of an interconnect metal layer, such as a first interconnect metal layer (i.e. “M1”) of a semiconductor wafer, can undesirably reduce the manufacturing yield of semiconductor devices, such as memory and logic devices.
In a conventional fabrication process, interconnect lines in a semiconductor device, such as a memory device, can be formed by patterning and etching trenches in a dielectric layer situated over a semiconductor wafer. A plating process can then be used to deposit a metal, such as copper, in the trenches and over the dielectric layer. A chemical mechanical polishing (CMP) process is typically used to remove excess metal over the trenches and form interconnect lines in the trenches. However, since temperature is higher at the center of the wafer compared to the edges of the wafer during the CMP process, more metal is removed in the center of the wafer than at the edges of the wafer. As a result, the thickness of the interconnect lines can vary significantly across the wafer, which can cause undesirable variations in sheet resistivity of the interconnect metal layer.
Thus, there is a need in the art for a method for reducing variations in sheet resistivity of an interconnect metal layer fabricated over a semiconductor wafer.